1. Field of the Invention
This invention relates generally to methods to control processes and to screen product and more particularly to a statistical process control method for using regression analysis and goodness of fit measurements to control processes and/or to screen devices and more particularly to a statistical process control method for using goodness of fit measurements to control electronic/semiconductor manufacturing processes, such as resistance and void defects in conductive lines.
2. Description of the Prior Art
During the fabrication of semiconductor devices, multiple film layers are deposited on a substrate. Preferably, the film layer should form a continuous coating of uniform thickness over the entire surface of the substrate. For example, a metal film layer may be used to cover a dielectric layer, wherein the dielectric layer includes holes or trenches extending therethrough. The metal film fills or conformally covers the holes or trenches in the dielectric layer to provide a conductive path through the dielectric layer to the layer or layers beneath the dielectric layer. After the metal film is deposited on the dielectric layer, it may then be masked and etched to form isolated metal interconnects on the substrate that extend above the base of any hole or trench by a height that approximately equals the sum of the thickness of the metal film deposited on the dielectric layer and the depth of the hole or trench.
To ensure that the interconnects formed on the substrate have the desired electrical properties, the thickness of the metal film layer deposited on the substrate must be maintained within a specified tolerance band. If the metal film is too thick or too thin, the height, and thus the electrical resistance, of the interconnects created on the substrate will fall outside of the desired tolerance range. Likewise, if the thickness of the film layer is substantially non-uniform, the electrical resistance of a potion of the interconnects will fall outside of the desired tolerance range. In these cases, the devices ultimately formed with the interconnects that fall outside of the tolerance range will be defective.
One method of method of monitoring the thickness of an electrically conductive film deposited on a semiconductor substrate is to measure the electrical sheet resistance of the film.
The sheet resistance of thin films is commonly measured with one of two different measuring apparatuses. A multi-point probe may be placed into contact with the film layer to measure the resistance of the film layer between the points, or a non-contacting eddy current probe may be placed in proximity with the substrate to measure the sheet resistance of the film layer. Based upon the sheet resistance value obtained for the film layer, in comparison with the tolerance band for the sheet resistance value and the prior sheet resistance values obtained from the same batch of substrates, a determination can be made as to whether any adjustments in the operating parameters of the deposition chamber need to be made.
Examples of a resistance measurement and a sheet resistivity measurement are provided here. Resistance can be measured on a two point structure (not shown). FIG. 1 shows schematically a four-point Kelvin technique in the prior art for measuring the resistance value of a device 1000 (e.g., a resistor) in an integrated circuit. In FIG. 1, device 1000 is connected to four terminals (pads) 1001-1004. According to the four-point Kelvin technique, a current I is forced through device 1000 via terminals 1001 and 1002, resulting in a voltage difference V1−V2 across device 1000. The voltage difference is measured across the other two terminals 6003 and 6004. The resistance R of device 1000 is provided by:R=(V1−V2)/I Sheet resistance Rs is a convenient measure of resistivity of a conducting layer.
FIG. 2 shows a Kelvin structure 2000 In Kelvin structure 2000, rectangular portion 2201 for which a resistance is measured. Rectangular portion 11201 has a length L which is much greater than its width W. A current I is forced across the length of rectangular portion 2201 via probe pads 2202 and 2203 to create a voltage difference ΔV=V1−V2 along the length of rectangular portion 2201, which is measured across probe pads 2204 and 2205. The sheet resistance (Rs) is thus determined by:Rs=ΔV/I*W/L 
By choosing a width W which is much larger than the minimal width Wmin for conductors in the layer in question (e.g., W=20*Wmin), Kelvin structure 1000 is relatively insensitive to CD loss. Further, by having a length L much greater than its width W, thereby raising its resistance R along length L, test structure 1000 maintains a relatively measurable voltage difference across probe pads 2204 and 2205, while avoiding excessive heating effects because of the relatively smaller current. Rectangular portion 2201 is provided only for illustrative purpose. In fact, the shape of the portion across which resistance is measured is not essential for achieving the results above. To provide the requisite measurable resistance, an effective length in the direction of current flow which is significantly greater than its effective width suffices. For example, region 2201 could be replaced with a serpentine resistive trace which has a total length greatly exceeding its width, provided that the resistive trace's width significantly exceeds the minimum width Wmin for the conductor layer. A field solver can be used to calculate the effective length-to-width ratio, and hence the relationship between R and Rs, using well-known techniques.
Resistance measurements are common methods to monitor and control the resistivity (sheet resistance) and width in semiconductor processing. However, the inventor has found resistance measurements are generally not sensitive enough to detect small, low level defects, such as void defects.
The semiconductor and electronics industry primarily depended on manual microscopic, and more recently, automated inspection techniques to find and screen defects. These techniques become less effective, however, as geometries continue to shrink into the deep submicron regime, since the size for which defects are critical also shrink. Defects such as interior voids in conductive lines are even more difficult to detect visually. Moreover, some defects, such as stress induced voids in Al lines, may not appear until several process steps after the Al conductors were inspected.
There is a need for an improved process control and device screening method to be sensitive to small variations in measured test values, such as sheet resistance.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,403,389B1 (Chang et al.) shows a method for measuring sheet resistance.
U.S. Pat. No. 5,627,101 (Lin et al.) shows a test method for electro-migration using a Metal and Poly test structure
U.S. Pat. No. 5,987,398 (Halverson et al.) shows a method for SPC for a process having a non-constant mean of a response variable.
U.S. Pat. No. 5,883,437 (Maruyama et al.) discloses a method for applying a time varying voltage between the electrode and wiring pattern at different locations.
U.S. Pat. No. 6,466,038 (Pekin, et al.) shows a method for non-isothermal electro-migration testing of interconnects.
U.S. Pat. No. 5,514,974 (Bouldin) shows a method for testing for metal failures by using 2 different test structures.
U.S. Pat. No. 6,087,189 (Huang) shows test structure to monitor silicide.
U.S. Pat. No. 5,552,718 (Bruce et al.) shows a test structure for space and line measurement.